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? 2010 semtech corporation 1 sc403 6a ecospeed tm integrated fet regulator with programmable ldo features power system: input voltage 3v to 28v internal or external bias voltage 3v to 5v integrated bootstrap switch programmable ldo output 200ma 1% reference tolerance -40 to +85 c ecospeed tm architecture with pseudo-fixed frequency adaptive on-time control logic input/output control: independent control en for ldo and switcher programmable v in uvlo threshold power good output selectable ultrasonic power save mode programmable soft start time protections: over-voltage and under-voltage tc compensated r ds(on) sensed current limit thermal shutdown any esr sp, poscap, oscon, and ceramic capacitors package: lead-free package 5x5mm, 32-pin mlpq fully rohs/weee compliant and halogen free applications ofce automation and computing networking and telecommunication equipment point of load power supplies and module replacement ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the sc403 is a stand-alone synchronous ecospeed tm buck power supply which incorporates semtechs advanced patent-pending adaptive on-time control architecture to provide excellent light-load efciency and fast transient response. it features integrated power mosfets, a boot - strap switch, and a programmable ldo in a 5x5mm package. the device is highly efcient and uses minimal pcb area. the sc403 supports using standard capacitor types such as electrolytic or special polymer, in addition to ceramic, at switching frequencies up to 1mhz. the programmable frequency, synchronous operation, and selectable power- save provide high efciency operation over a wide load range. additional features include a programmable soft-start, programmable cycle-by-cycle over-current limit protec - tion, under and over-voltage protections, soft shutdown, and selectable power-save. the device also provides sep - arate enable inputs for the pwm controller and ldo as well as a power good output for the pwm controller. the wide input and bias voltage ranges, programmable frequency, and programmable ldo make the device extremely flexible and easy to use in a broad range of applications. the sc402 can be used in server computers and single cell or multi-cell battery systems in addition to traditional dc power supply applications. june 30, 2010 power management rton sc 403 fb vout vdd vin ss bst p g n d lx pgood i l i m lxs e n / p s v enl l x b s t rilim cbst enable / psave enable ldo vext / ldo a g n d + rfb 1 rfb 2 vout cout l 1 cin vin pgood ton 1 f csoft 10 ? typical application circuit
sc403 2 pin confguration ordering information marking information sc 403 yyww xxxxxx xxxxxx agnd pad 1 vin pad 2 lx pad 3 e n l 32 t o n 31 a g n d 30 e n / p s v 29 l x s 28 i l i m 27 p g o o d 26 l x 25 24 lx lx 23 pgnd 22 pgnd 21 pgnd 20 pgnd 19 pgnd 18 pgnd 17 p g n d 16 p g n d 15 n c 14 l x b s t 13 n c 12 v i n 11 v i n 10 v i n 9 bst 8 fbl 5 ss 7 vin 6 vdd 3 agnd 4 fb 1 top view vout 2 notes: 1) available in tape and reel only. a reel contains 3000 devices. 2) lead-free package only. device is rohs/weee compliant and halogen free. yyww = date code xxxxxx = semtech lot number xxxxxx = semtech lot number sc403 mlpq-32; 5x5, 32 lead device package sc403mltrt (1)(2) mlpq-32 5x5 SC403EVB evaluation board
sc403 3 absolute maximum ratings lx to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 lx to pgnd (v) (transient 100ns max.) . . . . . . -2 to +30 vin to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 en/psv, pgood, ilim, to gnd (v) . . . . . . -0.3 to +(v dd + 0.3) ss, vout, fb, fbl, to gnd (v) . . . . . . . . . -0.3 to +(v dd + 0.3) vdd to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 ton to agnd (v) . . . . . . . . . . . . . . . . . . . . . -0.3 to +(vdd - 1.5) enl (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to v in bst to lx (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 bst to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35 agnd to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 recommended operating conditions input voltage (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28 vdd to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5 vout to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 to 5.5 thermal information storage temperature (c) . . . . . . . . . . . . . . . . . . . . -60 to +150 maximum junction temperature (c) . . . . . . . . . . . . . . . 150 operating junction temperature (c) . . . . . . -40 to +125 thermal resistance, junction to ambient (2) (c/w) high-side mosfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 low-side mosfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 pwm controller and ldo thermal resistance . . . . . 36 peak ir refow temperature (c) . . . . . . . . . . . . . . . . . . . . 260 exceeding the above specifcations may result in permanent damage to the device or device malfunction. operation outside of the parameters specifed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114. (2) calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer fr4 pcb with thermal vias under the exposed pad per jesd51 standards. unless specifed: v in =12v, t a = +25c for typ, -40 to +85 c for min and max, t j < 125c, v dd = +5v, per applicable detailed application circuit electrical characteristics parameter conditions min typ max units input supplies vin uvlo threshold (1) sensed at enl pin, rising edge 2.40 2.60 2.95 v sensed at enl pin, falling edge 2.235 2.40 2.565 vin uvlo hysteresis en/psv = high 0.2 v vdd uvlo threshold measured at vdd pin, rising edge 2.5 3.0 v measured at vdd pin, falling edge 2.4 2.9 vdd uvlo hysteresis 0.2 v vin supply current enl , en/psv = 0v, v in = 16v 8.5 20 a standby mode; enl=v dd , en/psv = 0v 130
sc403 4 electrical characteristics (continued) parameter conditions min typ max units input supplies (continued) vdd supply current enl , en/psv = 0v 3 7 a en/psv = v dd , no load (f sw = 25khz), v fb > 750mv 2 ma en/psv = v dd , no load (f sw = 25khz), v fb > 750mv 1 v dd = 5v, f sw = 250khz, en/psv = foating , no load 4 v dd = 3v, f sw = 250khz, en/psv = foating , no load 2.5 fb on-time threshold static v in and load, 0 to +85 c 0.744 0.750 0.756 v static v in and load, -40 to +85 c 0.742 0.758 v frequency range continuous mode operation 1000 khz minimum f sw , en/psv = v dd , no load 25 bootstrap switch resistance 10 ? switching mosfet resistance r dson high side fet 30 m? low side fet 10 timing on-time continuous mode operation, v in = 15v, v out = 5v, f sw = khz, r ton = 300k? 2386 2650 2915 ns 3v < v dd < 4.5v (2) minimum on-time 80 ns minimum of-time v dd = 5v 250 ns v dd = 3v 370 soft-start soft-start current 2.75 a soft-start voltage when v out reaches regulation 1.5 v analog inputs/outputs vout input resistance 500 k?
sc403 5 electrical characteristics (continued) parameter conditions min typ max units current sense zero-crossing detector threshold lx - pgnd -3 0 +3 mv power good power good threshold upper limit, v fb > internal 750mv reference +20 % lower limit, v fb < internal 750mv reference -10 % start-up delay time (between pwm enable and pgood going high) v dd = 3v, c ss = 10nf 7 ms v dd = 5v, c ss = 10nf 12 soft start threshold when pgood logic switches high 64 % fault (noise immunity) delay time 5 s leakage 1 a power good on-resistance 10 ? fault protection valley current limit v dd = 5v,r ilim = 6k ? 5.1 a v dd = 3v,r ilim = 6k ? 4.3 output under-voltage fault v fb with respect to internal 750 mv reference, 8 consecutive clocks -25 % smart power-save protection threshold v fb with respect to internal 750 mv reference +10 % over-voltage protection threshold v fb with respect to internal 750 mv reference +20 % over-voltage fault delay 5 s over-temperature shutdown 10 c hysteresis 155 c logic inputs/outputs logic input high voltage enl, minimum level 1 v logic input low voltage enl, maximum level 0.4 v en/psv input for psave operation maximum level expressed in % of v dd 100 % minimum level expressed in % of v dd 45 en/psv input for forced continuous operation maximum level expressed in % of v dd 42 % minimum level 1 v
sc403 6 electrical characteristics (continued) parameter conditions min typ max units logic inputs/outputs (continued) en/psv input for disabling switcher maximum level 0.4 v minimum level 0 en/psv input bias current en/psv= vdd or agnd -8 +8 a enl input bias current v in = 16v 11 18 a fbl, fb input bias current fbl, fb = vdd or agnd -1 +1 a linear regulator (the ldo is shorted to the vdd pin internally.) fbl accuracy ldo load = 10ma 0.735 0.75 0.765 v ldo current limit short-circuit protection, v in = 12v, v dd < 0.75v 65 ma start-up and foldback, v in = 12v, 0.75 < v dd < 90% of fnal v dd value 115 operating current limit, v in = 12v, v dd > 90% of fnal v dd value 135 200 ldo to vout switch-over threshold (3) -140 +140 mv ldo to vout non-switch-over threshold (3) -450 +450 mv ldo to vout switch-over resistance v out = +5v 2 ? ldo drop out voltage (4) from v in to v dd , v dd = +5v, i ldo = 100ma 1.2 v notes: (1) v in uvlo is programmable using a resistor divider from vin to enl to agnd pins. the enl voltage is compared to an internal reference. (2) for vdd less than 4.5v, the on-time may be limited by the vdd supply voltage and by the v in . see the ton limitation and vdd supply voltage section in the applications information. (3) the switch-over threshold is the maximum voltage diferential between the vdd and vout pins which ensures that ldo will internally switch- over to vout. the non-switch-over threshold is the minimum voltage diferential between the ldo and vout pins which ensures that ldo will not switch-over to vout. (4) the ldo drop out voltage is the voltage at which the ldo output drops 2% below the no load regulation value.
sc403 7 rton 130 k ? sc 403 fb 1 vout 2 vdd 3 agnd 4 fbl 5 vin 6 soft 7 bst 8 v i n 9 v i n 10 v i n 11 p g n d 15 p g n d 16 17 18 19 20 21 pgnd 22 lx 23 lx 24 l x 25 p g o o d 26 i l i m 27 l x s 28 e n / p s v 29 a g n d 30 t o n 31 e n l 32 n c 14 l x b s t 13 n c 12 v i n pad 2 agnd pad 1 lx pad 3 rilim 8 . 06 k ? rldo 2 75 k ? rldo 1 425 k ? cin 2 x 10 f ( see note ) rgnd 0 cbst 1 f vin + 12 v pgnd pgnd pgnd pgnd pgnd + 10 nf cff 100 pf l 1 1 . 5 h vout 1 . 5 v @ 6 a , 300 khz cout 330 f 9 m ? enable / psave enable ldo pgood 1 f internal ldo used as bias 3 . 3 nf component value manufacturer part number web cin 2 x 10 f / 25 v murata grm 32 dr 71 e 106 ka 12 l www . murata . com key components www . cyntec . com l 1 1 . 5 h / 6 . 7 m ? cyntec pcmb 065 t - 1 r 5 ms cout note : the quantity of 10 f input capacitors required varies with the application requirements . www . panasonic . com 330 f / 9 m ? panasonic eef - sx 0 e 331 er 1 f rfb 2 10 k ? rfb 1 10 k ? detailed application circuit-1
sc403 8 rton 130 k ? sc 403 fb 1 vout 2 vdd 3 agnd 4 fbl 5 vin 6 soft 7 bst 8 v i n 9 v i n 10 v i n 11 p g n d 15 p g n d 16 17 18 19 20 21 pgnd 22 lx 23 lx 24 l x 25 p g o o d 26 i l i m 27 l x s 28 e n / p s v 29 a g n d 30 t o n 31 e n l 32 n c 14 l x b s t 13 n c 12 v i n pad 2 agnd pad 1 lx pad 3 rilim 8 . 06 k ? cin 2 x 10 f ( see note ) rgnd 0 cbst 1 f vin + 12 v pgnd pgnd pgnd pgnd pgnd + 10 nf cff 100 pf l 1 1 . 5 h rfb 2 10 k ? vout 1 . 5 v @ 6 a , 300 khz cout 330 f 15 m ? enable / psave pgood 1 f external 5 v used as bias 3 . 3 nf 5 v component value manufacturer part number web cin 2 x 10 f / 25 v murata grm 32 dr 71 e 106 ka 12 l www . murata . com key components www . cyntec . com l 1 1 . 5 h / 6 . 7 m ? cyntec pcmb 065 t - 1 r 5 ms cout note : the quantity of 10 f input capacitors required varies with the application requirements . www . panasonic . com 330 f / 9 m ? panasonic eef - sx 0 e 331 er 10 ? 1 f rfb 1 10 k ? detailed application circuit-2
sc403 9 typical characteristics efciency vs. load forced continuous mode i out ( a dc ) e f f i c i e n c y ( % ) p l o s s ( w ) 0 20 40 60 80 100 0 . 001 0 . 010 0 . 100 1 . 000 10 . 000 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 p loss efficiency v in = 6 v v in = 12 v v in = 20 v v in = 6 v v in = 20 v v in = 12 v characteristics in this section are based on using the applicable detailed application circuit. v out vs. load psave mode i out ( a dc ) v o u t ( v d c ) v p k p k ( m v r m s ) 1 . 425 1 . 450 1 . 475 1 . 500 1 . 525 1 . 550 1 . 575 0 . 001 0 . 010 0 . 100 1 . 000 10 . 000 0 25 50 75 100 125 150 v pk - pk v out v in = 12 v v in = 20 v v in = 6 v v in = 6 v v in = 20 v v in = 12 v efciency vs. load psave mode i out ( a dc ) e f f i c i e n c y ( % ) p l o s s ( w ) 0 20 40 60 80 100 0 . 001 0 . 010 0 . 100 1 . 000 10 . 000 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 efficiency p loss v in = 12 v v in = 20 v v in = 6 v v in = 12 v v in = 6 v v in = 20 v v out = 1.5v, v ldo = v dd = enl = 5v, en/p5v is foating v out vs. load forced continuous mode i out ( a dc ) v o u t ( v d c ) v p k p k ( m v r m s ) 1 . 425 1 . 450 1 . 475 1 . 500 1 . 525 1 . 550 1 . 575 0 . 001 0 . 010 0 . 100 1 . 000 10 . 000 0 25 50 75 100 125 150 v pk - pk v out v in = 12 v v in = 12 v v in = 6 v v in = 20 v v in = 6 v v in = 20 v v out = 1.5v, v ldo = v dd = enl = 5v, en/p5v is foating v out = 1.5v, v ldo = v dd = en/psv= enl = 5v v out = 1.5v, v ldo = v dd = en/psv= enl = 5v
sc403 10 typical characteristics (continued) v in ( v dc ) v p k _ p k ( m v r m s ) v o u t ( v d c ) 1 . 425 1 . 450 1 . 475 1 . 500 1 . 525 1 . 550 1 . 575 6 . 0 8 . 8 11 . 5 14 . 3 17 . 0 19 . 8 22 . 5 25 . 3 28 . 0 0 25 50 75 100 125 150 v out v pkpk characteristics in this section are based on using the applicable detailed application circuit. v out vs. line forced continuous mode frequency vs. load forced continuous mode i out ( a dc ) f r e q u e n c y ( k h z ) 0 50 100 150 200 250 300 350 400 0 . 001 0 . 010 0 . 100 1 . 000 10 . 000 v in = 12 v v in = 20 v v in = 6 v frequency vs. load psave mode i out ( a dc ) f r e q u e n c y ( k h z ) 0 50 100 150 200 250 300 350 400 0 . 001 0 . 010 0 . 100 1 . 000 10 . 000 v in = 12 v v in = 6 v v in = 20 v frequency vs. line fcm mode v in ( v dc ) f r e q u e n c y ( h z ) 0 50 100 150 200 250 300 350 400 6 . 0 8 . 8 11 . 5 14 . 3 17 . 0 19 . 8 22 . 5 25 . 3 28 . 0 v out = 1.5v, v ldo = v dd = enl = 5v, en/p5v is foating v out = 1.5v, v ldo = v dd = enl = 5v, en/p5v is foating v out = 1.5v, v ldo = v dd = enl = 5v, en/p5v is foating v out = 1.5v, v ldo = v dd = en/psv= enl = 5v on time vs. line 0 200 400 600 800 1000 1200 6 . 0 8 . 8 11 . 5 14 . 3 17 . 0 19 . 8 22 . 5 25 . 3 28 . 0 input voltage ( v ) o n - t i m e ( n s ) 5 v 3 . 3 v v out = 1.5v, v ldo = v dd = enl = 5v, i out = 0a
sc403 11 ultrasonic powersave mode no load time (10s/div) (20mv/div) (10v/div) v in = 12v, v out = 1.5v, i out = 0a, v ldo = v dd = en/psv= enl = 3.3v forced continuous mode no load time (10s/div) (20mv/div) (10v/div) v in = 12v, v out = 1.5v, i out = 0a, v ldo = v dd = enl = 3.3v, en/psv= foating typical characteristics (continued) characteristics in this section are based on using the applicable detailed application circuit. time (400s/div) self-biased start-up power good true (10v/div) (2v/div) (5v/div) v in = 0v to 12v step, v out = 1.5v, i out = 0a, v ldo = v dd = en/psv= enl = 3.3v (500mv/div) time (400s/div) enabled loaded output (10mv/div) (2v/div) (5v/div) v in = 12v, v out = 1.5v, i out = 1a, v ldo = v dd = enl = en/psv= foating (500mv/div)
sc403 12 typical characteristics (continued) characteristics in this section are based on using the applicable detailed application circuit. transient response time (40s/div) (10mv/div) (50mv/div) (5a/div) v in = 12v, v out = 1.5v, i out = 0a to 7a, v ldo = v dd = en/psv= enl = 3.3v output over-current response normal operation time (100s/div) (500mv/div) (10v/div) (5a/div) (5v/div) v in = 12v, v out = 1.5v, v ldo = v dd = enl = 3.3v, en/psv= foating; i out ramped to trip point output under-voltage response normal operation time (100s/div) (500mv/div) (10v/div) (5v/div) v in = 12v, v out = 1.5v, i out = 0a, v ldo = v dd = enl = 3.3v, foating en/psv shorted output response soft-start operation time (400s/div) (1v/div) (5v/div) (10a/div) (5v/div) v in = 12v, v out = 1.5v, i out = 0a, v ldo = v dd = en/psv= enl = 3.3v shorted output response normal operation time (40s/div) (1v/div) (10v/div) (10a/div) (5v/div) v in = 12v, v out = 1.5v, v ldo = v dd = enl = 3.3v, en/p5v is foating
sc403 13 pin descriptions pin # pin name pin function 1 fb feedback input for switching regulator used to program the output voltage connect to an external resis - tor divider from vout to agnd. 2 vout switcher output voltage sense pin also the input to the internal switch-over between vout and vldo. the voltage at this pin must be less than or equal to the voltage at the vdd pin. 3 vdd bias supply for the ic when using the internal ldo as a bias power supply, the vdd is the ldo output. when using an external power supply to bias the ic, the ldo output should be disabled. 4, 30, pad 1 agnd analog ground 5 fbl feedback input for the internal ldo connect to an external resistor divider from vdd to agnd to pro - gram the ldo output. 6, 9-11, pad 2 vin input supply voltage 7 ss the soft start time is programmed by an internal current source charging a capacitor on this pin. 8 bst bootstrap pin connect a capacitor of at least 100nf from bst to lx to develop the foating supply for the high-side gate drive. 12 nc no connection 13 lxbst lx boost connect to the bst capacitor. 23-25, pad 3 lx switching (phase) node 14 nc no connection 15-22 pgnd power ground 26 pgood open-drain power good indicator high impedance indicates power is good. an e xternal pull-up resistor is required. 27 ilim current limit sense pin used to program the current limit by connecting a resistor from ilim to lxs. 28 lxs lx sense connects to r ilim . 29 en/psv enable/power-save input for the switching regulator connect to agnd to disable the switching regulator. float to operate in forced continuous mode (psave disabled). connect to vdd to operate with ultrasonic psave mode enabled. 31 ton on-time programming input set the on-time by connecting through a resistor to agnd. 32 enl enable input for the ldo connect enl to agnd to disable the ldo. drive with logic signal for logic con - trol, or program the vin uvlo with a resistor divider between vin, enl, and agnd pins.
sc403 14 block diagram reference soft start fb agnd on - time generator control & status pgood gate drive control vin pgnd ton vout zero cross detector valley current limit ilim enl fbl vldo switchover mux a y b ldo vdd bst fb comparator - lx en / psv bypass comparator bypass comparator nc nc a 12 8 27 14 32 5 3 2 31 1 26 29 a = connected to pins 6 , 9 - 11 , pad 2 b = connected to pins 23 - 25 , pad 3 c = connected to pins 15 - 22 d = connect to pins 4 , 30 , pad 1 b c d v in vdd vdd v in bootstrap switch lo - side mosfet hi - side mosfet lxbst 13 lxs 28 dl dl vdd vdd vdd ss 7
sc403 15 synchronous buck converter the sc403 is a step down synchronous dc-dc buck con - verter with integrated power mosfets and a 200ma pro - grammable ldo. the device operates at a current up to 6a at very high efciency. a space saving 5x5 (mm) 32-pin package is used. the programmable operating frequency of up to 1mhz enables optimizing the confguration for pcb area and efciency. the buck controller uses a pseudo-fxed frequency adap - tive on-time control. this control method allows fast tran - sient response which permits the use of smaller output capacitors. input voltage requirements the sc403 requires two input supplies for normal opera - tion: v in and v dd . v in operates over a wide range from 3v to 28v. vdd requires a supply voltage between 3v to 5v that can be an external source or the internal ldo from v in . power up sequence the sc403 initiates a start up when vin, vdd, and en/psv pins are above the applicable thresholds. when using an external bias supply for the v dd voltage, it is recommended that the v dd is applied to the device only after the v in voltage is present because v dd cannot exceed v in at any time. a 10? resistor must be placed between the external v dd supply and the vdd pin to avoid damage to the device during power-up and or shutdown situations where v dd could exceed v in unexpectedly. shutdown the sc403 can be shutdown by pulling either vdd or en/ psv pin below its threshold. when using an external supply voltage for v dd , the vdd pin must be deactivated while the v in voltage is still present. a 10? resistor must be placed between the external v dd supply and the vdd pin to avoid damage to the device. when the vdd pin is active and en/psv is at low logic level, the output voltage discharges through an internal fet. psuedo-fxed frequency adaptive on-time control the pwm control method used by the sc403 is pseudo- fxed frequency, adaptive on-time, as shown in figure 1. the ripple voltage generated at the output capacitor esr is used as a pwm ramp signal. this ripple is used to trigger the controller on-time. q 1 q 2 l c out esr + c in v out fb threshold v fb v lx v lx ton fb v in figure 1 pwm control method, v out ripple the adaptive on-time is determined by an internal one- shot timer. when the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the high- side mosfet. the pulse period is determined by v out and v in . the period is proportional to output voltage and inversely proportional to input voltage. with this adaptive on-time arrangement, the device automatically antici - pates the on-time needed to regulate v out for the present v in condition and at the selected frequency. the advantages of adaptive on-time control are: predictable operating frequency compared to other variable frequency methods. reduced component count by eliminating the error amplifer and compensation components. reduced component count by removing the need to sense and control inductor current. fast transient response the response time is controlled by a fast comparator instead of a typi - cally slow error amplifer. reduced output capacitance due to fast tran - sient response ? ? ? ? ? applications information
sc403 16 one-shot timer and operating frequency one-shot timer operation is shown in figure 2. the fb comparator output goes high when v fb is less than the internal 750mv reference. this feeds into the gate drive and turns on the high-side mosfet, and starts the one- shot timer. the one-shot timer uses an internal compara - tor and a capacitor. one comparator input is connected to v out , the other input is connected to the capacitor. when the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to v in . when the capacitor voltage reaches v out , the on-time is completed and the high-side mosfet turns of. gate drives fb comparator one - shot timer on - time = k x r ton x ( v out / v in ) v out v in fb 750 mv q 1 q 2 l c out v in esr + v out v lx fb dh dl r ton + - figure 2 on-time generation this method automatically produces an on-time that is proportional to v out and inversely proportional to v in . under steady-state conditions, the switching frequency can be determined from the on-time by the following equation. in on out sw v t v f u the sc403 uses an external resistor to set the on-time which indirectly sets the frequency. the on-time can be programmed to provide an operating frequency from 200khz to 1mhz using a resistor between the ton pin and ground. the resistor value is selected by the following equation. out in on ton v pf 25 v ) ns 10 t ( r u u the maximum r ton value allowed is shown by the follow - ing equation. a 5 . 1 10 v r min _ in max _ ton p u immediately after the on-time, the dl (drive signal for the low side fet) output drives high to turn on the low-side mosfet. dl has a minimum high time of ~320ns, after which dl continues to stay high until one of the following occurs: vfb falls below the 750mv reference the zero cross detector senses that the voltage on the lx node is below ground. power save is activated eight cycles after a zero crossing is detected. ton limitations and v dd supply voltage for v dd below 4.5v, the ton accuracy may be limited by the input voltage. the original r ton equation is accurate if v in satisfes the relationship over the entire v in range, as follows. v in < (v dd - 1.6v) x 10 if v in exceeds ( v dd - 1.6v) x 10, for all or part of the v in range, the r ton equation is not accurate. in all cases where v in > ( v dd - 1.6v) x 10, the r ton equation must be modifed, as follows. out dd on ton v 25pf 10 1.6v) (v 10ns) (t r u u u note that when v in > ( v dd - 1.6v) x 10 , the actual on-time is fxed and does not vary with v in . when operating in this condition, the switching frequency will vary inversely with v in rather than approximating a fxed frequency. v out voltage selection the switcher output voltage is regulated by comparing v out as seen through a resistor divider at the fb pin to the internal 750mv reference voltage, see figure 3. r 1 to fb pin r 2 v out figure 3 output voltage selection ? ? applications information (continued)
sc403 17 note that this control method regulates the valley of the output ripple voltage, not the dc value. the dc output voltage v out is ofset by the output ripple according to the following equation. ? 1 ? ? ? 1 ? u 2 v r r 1 75 . 0 v ripple 2 1 out when a large capacitor is placed in parallel with r1 (c top ) v out is shown by the following equation. 2 top 1 2 1 2 2 top 1 ripple 2 1 out c r r r r 1 ) c r ( 1 2 v r r 1 75 . 0 v ? ? 1 ? z u z u ? 1 ? ? ? 1 ? u enable and power save input the en/psv input is used to enable or disable the switch - ing regulator and the ldo. when en/psv is low (grounded), the switching regulator is of and in its lowest power state. when of, the output of the switching regulator soft-dis - charges the output into a 15? internal resistor via the v out pin. when en/psv is allowed to foat, the pin voltage will foat to 33% of the voltage at vdd. the switching regula - tor turns on with psave (power save) disabled and all switching is in forced continuous mode. when en/psv is high (above 45% of the voltage at vdd), the switching regulator turns on with ultrasonic power- save enabled. the ultrasonic psave operation maintains a minimum switching frequency of 25khz, for applications with stringent audio requirements. forced continuous mode operation the sc403 operates the switcher in fcm (forced continuous mode) by foating the en/psv pin (see figure 4). in this mode one of the power mosfets is always on, with no intentional dead time other than to avoid cross- conduction. this feature results in uniform frequency across the full load range with the trade-of being poor efciency at light loads due to the high-frequency switch - ing of the mosfets. dh is the gate signal driving the upper mosfet. dl is the lower gate signal driving the lower mosfet. fb ripple voltage ( v fb ) fb threshold dl dh inductor current dc load current dh on - time is triggered when v fb reaches the fb threshold . ( 750 mv ) on - time ( t on ) dl drives high when on - time is completed . dl remains high until v fb falls to the fb threshold . figure 4 forced continuous mode operation ultrasonic psave operation the sc403 provides ultrasonic psave operation at light loads, with the minimum operating frequency fixed at 25khz. this is accomplished using an internal timer that monitors the time between consecutive high-side gate pulses. if the time exceeds 40s, dl drives high to turn the low-side mosfet on. this draws current from v out through the inductor, forcing both v out and v fb to fall. when v fb drops to the 750mv threshold, the next dh on-time is trig - gered. after the on-time is completed the high-side mosfet is turned of and the low-side mosfet turns on. the low-side mosfet remains on until the inductor current ramps down to zero, at which point the low-side mosfet is turned of. applications information (continued)
sc403 18 because the on-times are forced to occur at intervals no greater than 40s, the frequency will not fall below ~25khz. figure 5 shows ultrasonic psave operation. fb ripple voltage ( v fb ) fb threshold ( 750 mv ) inductor current ( 0 a ) minimum f sw ~ 20 khz dh dh on - time is triggered when v fb reaches the fb threshold on - time ( t on ) dl 50 sec time - out after the 50 sec time - out , dl drives high if v fb has not reached the fb threshold . figure 5 ultrasonic psave operation smart psave protection active loads may leak current from a higher voltage into the switcher output. under light load conditions with psave enabled, this can force v out to slowly rise and reach the over-voltage threshold, resulting in a hard shutdown. smart psave prevents this condition. when the fb voltage exceeds 10% above nominal, the device immediately dis - ables psave, and dl drives high to turn on the low-side mosfet. this draws current from v out through the induc - tor and causes v out to fall. when v fb drops back to the 750mv trip point, a normal t on switching cycle begins. this method prevents a hard ovp shutdown and also cycles energy from v out back to v in . it also minimizes operating power by avoiding forced conduction mode operation. figure 6 shows typical waveforms for the smart psave feature. fb threshold high - side drive ( dh ) low - side drive ( dl ) v out drifts up to due to leakage current flowing into c out dh and dl off dl turns on when smart psave threshold is reached smart power save threshold ( 825 mv ) dl turns off when fb threshold is reached single dh on - time pulse after dl turn - off v out discharges via inductor and low - side mosfet normal dl pulse after dh on - time pulse normal v out ripple figure 6 smart psave smartdrive tm for each dh pulse the dh driver initially turns on the high- side mosfet at a lower speed, allowing a softer, smooth turn-of of the low-side diode. once the diode is of and the lx voltage has risen 1v above pgnd, the smartdrive circuit automatically drives the high-side mosfet on at a rapid rate. this technique reduces switching power loss while maintaining high efficiency and also avoids the need for snubbers or series resistors in the gate drive. current limit protection programmable current limiting is accomplished by using the rds on of the lower mosfet for current sensing. the current limit is set by the r ilim resistor. the r ilim resistor con - nects from the ilim pin to the lxs pin which is also the drain of the low-side mosfet. when the low-side mosfet is on, an internal ~10 a current flows from the ilim pin and through the r ilim resistor, creating a voltage drop across the resistor. while the low-side mosfet is on, the inductor current fows through it and creates a voltage across the rds on . the voltage across the mosfet is negative with respect to ground. if this mosfet voltage drop exceeds the voltage across r ilim , the voltage at the ilim pin will be nega - tive and current limit will activate. the current limit then keeps the low-side mosfet on and will not allow another high-side on-time, until the current in the low-side mosfet reduces enough to bring the ilim voltage back up to zero. this method regulates the inductor valley current at the level shown by ilim in figure 7. applications information (continued)
sc403 19 time i peak i load i lim i n d u c t o r c u r r e n t figure 7 valley current limit setting the valley current limit to 6a results in a peak induc - tor current of 6a plus the peak-to-peak ripple current. in this situation, the average (load) current through the induc - tor is 6a plus one-half the peak-to-peak ripple current. the internal 10 a current source is temperature compen - sated at 4100ppm in order to provide tracking with the rds on . the r ilim value is calculated by the following equation. r ilim = 1176 x i lim x [0.088 x (5v - v dd ) + 1] ( ? ) where i lim is in amps. when selecting a value for r ilim do not exceed the absolute maximum voltage value for the ilim pin. note that because the low-side mosfet with low rds on is used for current sensing, the pcb layout, solder connections, and pcb connec - tion to the lx node must be done carefully to obtain good results. r ilim should be connected directly to lxs (pin 28). soft-start of pwm regulator sc403 has a programmable soft-start time that is con - trolled by an external capacitor at the ss pin. after the controller meets both uvlo and en/psv thresholds, the controller has an internal current source of 2.75a fowing through the ss pin to charge the capacitor. during the start up process (figure 8), 50% of the voltage at the ss pin is used as the reference for the fb comparator. the pwm comparator issues an on-time pulse when the voltage at the fb pin is less than 50% of the ss pin. as result, the output voltage follows the ss start voltage. the output voltage reaches and maintains regulation when the soft start voltage is > 1.5v. the time between the frst lx pulse and when v out meets regulation is the soft start time (t ss ). the calculation for the soft-start time is shown by the following equation. a 75 . 2 v 5 . 1 c t ss ss p u the voltage at the ss pin continues to ramp up and eventu - ally is equal to 64% of v dd . after soft start completes, the fb pin voltage is compared to an internal reference of 0.75v. the delay time between the v out regulation point and pgood going high is shown by the following equation. a 75 . 2 v 5 . 1 v 64 . 0 t dd delay - pgood p u time (400s/div) (10mv/div) (2v/div) (5v/div) (500mv/div) figure 8 soft-start timing diagram pre-bias startup sc403 can start up as if in a soft-start condition with an existing output voltage level. the soft start time is still the same as normal start up (when the output voltage starts from zero). the output voltage starts to ramp up when one-half of the voltage at ss pin meets the pre-charge fb voltage level. pre-bias startup is achieved by turning of the lower gate when the inductor current falls below zero. this method prevents the output voltage from decreasing. power good output the pgood (power good) output is an open-drain output which requires a pull-up resistor. when the voltage at the fb pin is 10% below the nominal voltage, pgood is pulled low. it is held low until the output voltage returns above 92% of nominal. pgood will transition low if the v fb pin exceeds +20% of nominal, which is also the over-voltage shutdown thresh - old. pgood also pulls low if the en/psv pin is low when v dd voltage is present. applications information (continued)
sc403 20 output over-voltage protection over-voltage protection becomes active as soon as the device is enabled. the threshold is set at 750mv + 20% (900mv). when v fb exceeds the ovp threshold, dl latches high and the low-side mosfet is turned on. dl remains high and the controller remains of, until the en/psv input is toggled or vdd is cycled. there is a 5s delay built into the ovp detector to prevent false transitions. pgood is also low after an ovp event. output under-voltage protection when v fb falls 25% below its nominal voltage (falls to 562.5mv) for eight consecutive clock cycles, the switcher is shut of and the dh and dl drives are pulled low to tri- state the mosfets. the controller stays of until en/psv is toggled or vdd is cycled. vdd uvlo, and por uvlo (under-voltage lock-out) circuitry inhibits switch - ing and tri-states the dh/dl drivers until v dd rises above 3.0v. an internal por (power-on reset) occurs when v dd exceeds 3.0v, which resets the fault latch and soft-start counter to prepare for soft-start. the sc403 then begins a soft-start cycle. the pwm will shut of if vdd falls below 2.4v. ldo regulator sc403 has an option to bias the switcher by using an inter - nal ldo from v in . the ldo output is connected to vdd internally. the output of the ldo is programmable by using external resistors from the vdd pin to agnd. the feedback pin (fbl) for the ldo is regulated to 750mv (see figure 9). r ldo 1 to fbl pin vdd r ldo 2 figure 9 ldo start-up the ldo output voltage is set by the following equation. ? ? 1 ? u 2 ldo 1 ldo r r 1 mv 750 vldo a minimum 0.1f capacitor referenced to agnd is required along with a minimum 1.0f capacitor refer - enced to pgnd to flter the gate drive pulses. refer to the layout guidelines section for component placement suggestions. ldo enl functions the enl input is used to control the internal ldo. when enl is low (grounded), the ldo is of. when enl is above the v in uvlo threshold, the ldo is enabled and the switcher is also enabled if en/psv and vdd meet the thresholds. the enl pin also acts as the switcher uvlo (under-voltage lockout) for the v in supply. the v in uvlo voltage is pro - grammable via a resistor divider at the vin, enl and agnd pins. if the enl pin transitions from high to low within 2 switch - ing cycles and is less than 1v, then the ldo will turn of but the switcher remains on. if the enl goes below the v in uvlo threshold and stays above 1v, then the switcher will turn of but the ldo remains on. the v in uvlo function has a typical threshold of 2.6v on the v in rising edge. the falling edge threshold is 2.4v. note that it is possible to operate the switcher with the ldo disabled, but the enl pin must be below the logic low threshold (0.4v maximum). in this case, the uvlo function for the input voltage cannot be used. the table below summarizes the function of the enl and en pins, with respect to the rising edge of enl. en enl ldo status switcher status low low, < 0.4v of of high low, < 0.4v of on low high, < 2.6v on of high high, < 2.6v on of low high, > 2.6v on of high high, > 2.6v on on applications information (continued)
sc403 21 figure 10 shows the enl voltage thresholds and their efect on ldo and switcher operation. agnd enl low threshold ( min 0 . 4 v ) 2 . 6 v 2 . 4 v ldo on ldo on ldo off v in uvlo hysteresis enl voltage switcher on if en = high switcher on if en = high switcher off by v in uvlo figure 10 enl threshold before start-up, the ldo checks the status of the following signals to ensure proper operation can be maintained. enl pin v in input voltage when the enl pin is high and v in is above the uvlo point, the ldo will begin start-up. during the initial phase, when the v dd voltage (which is the ldo output voltage) is less than 0.75v, the ldo initiates a current-limited start-up (typically 65ma) to charge the output capacitors while protecting from a short circuit event. when v dd is greater than 0.75v but still less than 90% of its final value (as sensed at the fbl pin), the ldo current limit is increased to ~115ma. when v dd has reached 90% of the fnal value (as sensed at the fbl pin), the ldo current limit is increased to ~200ma and the ldo output is quickly driven to the nominal value by the internal ldo regulator. it is recom - mended that during ldo start-up to hold the pwm switching of until the ldo has reached 90% of the fnal value. this prevents overloading the current-limited ldo output during the ldo start-up. due to the initial current limitations on the ldo during power up (figure 11), any external load attached to the vdd pin must be limited to 20ma before the ldo has reached 90% of it fnal regulation value. 1. 2. v vldo final 90 % of v vldo final constant current startup @ ~ 115 ma voltage regulating with ~ 200 ma current limit short - circuit protection @ ~ 65 ma 0 . 7 v figure 11 ldo start-up ldo switch-over operation the switch-over function is provided to increase efciency by using the more efcient dc-dc converter to power the ldo output, avoiding the less efficient ldo regulator when possible. the switch-over function connects the vdd pin directly to the vout pin using an internal switch. when the switch-over is complete the ldo is turned of, which results in power savings and maximizes efciency. if the ldo output is used to bias the sc403, then after switch-over the device is self-powered from the switching regulator with the ldo turned of. the switch-over logic waits for 32 switching cycles before it starts the switch-over. when the ldo is already in regu - lation and the dc-dc converter is later enabled, as soon as the pgood output goes high, the 32 cycles are started. the voltages at the vdd and vout pins are then com - pared; if the two voltages are within 300mv of each other, the vdd pin connects to the vout pin using an internal switch, and the ldo is turned of. switch-over limitations on vout, enl, and vdd because the internal switch-over circuit always compares the vout and vdd pins at start-up, there are limitations on permissible combinations of these pins. consider the case where v out is programmed to 3.0v and v ldo is pro - grammed to 3.3v. after start-up, the device would connect vout to vdd and disable the ldo, since the two voltages are within the 300mv switch-over window. to avoid unwanted switch-over, the minimum diference between the voltages for v out and v ldo should be 500mv. applications information (continued)
sc403 22 applications information (continued) in many applications, the en/psv pin will be pulled high to the vdd node to allow control of the pwm and ldo enl pin. if the switch over feature is used, this circuit must be implemented with caution or the circuit may be damaged. in the case where the enl pin is being controlled by a gpio signal or is tied directly to the input voltage, the enl pin can be pulled low while the pwm is still generating an output voltage that is seen across one of the switch-over diodes. this may result in the vdd node being held above its uvlo threshold while the ldo is deactivated. operating in this way can potentially damage the part. in the case where the enl pin is used to control the input uvlo, it is acceptable to connect en/psv directly to the vdd node. it is not recommended to use the switch-over feature for an output voltage less than 3v since this does not provide sufcient voltage for the gate-source drive to the internal p-channel switch-over mosfet. switch-over mosfet parasitic diode the switch-over mosfet contains a parasitic diode that is inherent to its construction, as shown in figure 12. switchover mosfet parasitic diode vdd ldo v out switchover control figure 12 switch-over mosfet parasitic diodes if v out is higher than vdd, then the diode will turn on and the sc403 operating current will fow through this diode. this has the potential of damaging the device. there are some important design rules that must be fol - lowed to prevent forward bias of this diode. the following condition, v dd v out needs to be satisfed in order for the parasitic diode to stay off and prevent damaging the device. many applications connect the en pin to v5v and control the on/of of the ldo and pwm simultaneously with the enl pin. this allows one signal to control both the bias and power output of the sc414. when v out > 3.0v this confguration can cause problems due to the parasitic diodes in the ldo switchover circuitry. after the v out > 3.0v pwm output is up and running the switchover diodes can hold up v5v > uvlo even if the enl pin is grounded, turning of the ldo. operating in this way can potentially damage the part. design procedure when designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specifed. the maximum input voltage (v inmax ) is the highest speci - fed input voltage. the minimum input voltage ( v inmin ) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and pcb traces. the following parameters defne the design. nominal output voltage (v out ) static or dc output tolerance transient response maximum load current (i out ) there are two values of load current to evaluate con - tinuous load current and peak load current. continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. peak load current determines instantaneous component stresses and fltering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. the following values are used in this design. v in = 12v + 10% v out = 1.5v + 4% f sw = 300khz load = 6a maximum frequency selection selection of the switching frequency requires making a trade-of between the size and cost of the external flter components (inductor and output capacitor) and the power conversion efciency. ? ? ? ? ? ? ? ?
sc403 23 applications information (continued) the desired switching frequency is 300khz which results from using components selected for optimum size and cost. a resistor (r ton ) is used to program the on-time (indirectly setting the frequency) using the following equation. out in on ton v pf 25 v ) ns 10 t ( r u u to select r ton , use the maximum value for v in , and for t on use the value associated with maximum v in . sw inmax out on f v v t u t on = 379 ns at 13.2v in , 1.5v out , 300khz substituting for r ton results in the following solution. r ton = 129.9k ? , use r ton = 130k ? inductor selection in order to determine the inductance, the ripple current must frst be defned. low inductor values result in smaller size but create higher ripple current which can reduce ef - ciency. higher inductor values will reduce the ripple current and ripple voltage and for a given dc resistance are more efcient. however, larger inductance translates directly into larger packages and higher cost. cost, size, output ripple, and efciency are all used in the selection process. the ripple current will also set the boundary for psave operation. the switching will typically enter psave mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 4a then psave operation will typically start for loads less than 2a. if ripple current is set at 40% of maximum load current, then psave will start for loads less than 20% of maximum current. the inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum load current. this provides an optimal trade-of between cost, efciency, and transient performance. during the dh on-time, voltage across the inductor is (v in - v out ). the equation for determining inductance is shown next. ripple on out in i t ) v v ( l u example in this example, the inductor ripple current is set equal to 50% of the maximum load current. therefore ripple current will be 50% x 6a or 3a. to find the minimum inductance needed, use the v in and t on values that corre - spond to v inmax . h 48 . 1 a 3 ns 379 ) 5 . 1 2 . 13 ( l p u a slightly larger value of 1.5h is selected. this will decrease the typical i ripple to 2.7a. note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current. the ripple current under minimum v in conditions is also checked using the following equations. ns 461 ns 10 v v r pf 25 t inmin out ton vinmin _ on u u l t ) v v ( i on out in ripple u a 38 . 2 ) 2 . 0 1 ( h 5 . 1 ns 461 ) 5 . 1 8 . 10 ( i min _ ripple u p u a 7 . 3 ) 2 . 0 1 ( h 5 . 1 ns 379 ) 5 . 1 8 . 10 ( i max _ ripple u p u the value of l has been adjusted by + 20% for the equa - tions above assuming an inductor tolerance of + 20%. output capacitor selection the output capacitors are chosen based upon required esr and capacitance. the maximum esr requirement is controlled by the output ripple requirement and the dc tolerance. the output voltage has a dc value that is equal to the valley of the output ripple plus 1/2 of the peak-to- peak ripple. a change in the output ripple voltage will lead to a change in dc voltage at the output.
sc403 24 applications information (continued) the design goal is that the output voltage regulation be 4% under static conditions. the internal 750mv refer - ence tolerance is 1%. allowing 1% tolerance from the fb resistor divider, this allows 2% tolerance due to v out ripple. since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 60mv for a 1.5v output. the maximum ripple current of 3.7a creates a ripple voltage across the esr. the maximum esr value allowed is shown by the following equations. a 7 . 3 mv 60 i v esr ripplemax ripple max esr max = 16.2 m ? the output capacitance is usually chosen to meet tran - sient requirements. a worst-case load release, from maximum load to no load at the exact moment when the inductor current is at the peak, determines the required capacitance. if the load release is instantaneous (load changes from maximum to zero in < 1s), the output capacitor must absorb all the inductors stored energy. this will cause a peak voltage on the capacitor requiring a capacitance provided by the following equation. 2 out 2 peak 2 ripplemax out min v v i 2 1 i l cout ? 1 ? u assuming a peak voltage v peak of 1.6v (100mv rise upon load release), and a 6a load release, the required capaci - tance is shown by the next equation. 2 2 2 min v 5 . 1 v 6 . 1 a 7 . 3 2 1 a 6 h 5 . 1 cout ? 1 ? u p cout min = 298f if the load release is relatively slow, the output capacitance can be reduced. at heavy loads during normal switching, when the fb pin is above the 750mv reference, the dl output is high and the low-side mosfet is on. during this time, the voltage across the inductor is approximately -v out . this causes a down-slope or falling di/dt in the inductor. if the load di/dt is not much faster than the -di/dt in the inductor, then the inductor current will tend to track the falling load current. this will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. the following can be used to calculate the needed capaci - tance for a given di load /dt. peak inductor current is shown by the next equation. i lpk = i max + 1/2 x i ripplemax i lpk = 6 + 1/2 x 3.7 = 7.9a dt dl current load of change of rate load i max = maximum load release = 6a out pk load max out lpk lpk out v v 2 dt dl i v i l i c u u u example s 1 a 2 dt dl load p this would cause the output current to move from 6a to 0a in 3.0s, giving the minimum output capacitance requirement shown in the following equation. v 5 . 1 v 6 . 1 2 s 1 2 6 5 . 1 9 . 7 h 5 . 1 a 9 . 7 c out p u u p u c out = 194 f note that c out is much smaller in this example, 194f compared to 298f based on a worst-case load release. to meet the maximum design criteria of minimum 298f and maximum 16m ? esr , select one capacitor rated at 330f and 9m ? esr . it is recommended that an additional small capacitor be placed in parallel with c out in order to flter high frequency switching noise.
sc403 25 applications information (continued) soft start capacitor selection for a soft-start time (t ss ) of approximately 3ms, solve the following equation for c ss . nf 5 . 5 c v 5 . 1 a 75 . 2 t c ss ss ss p if c ss is selected as 4.7 nf, then t ss will be 2.6 ms. then the pgood delay, the time from v out regulation to pgood signal high is shown by the following equation. a 75 . 2 ) v 5 . 1 v 64 . 0 ( nf 7 . 4 t dd delay - pgood p u at v dd = 5v, the pgood delay will be 2.9ms. stability considerations unstable operation is possible with adaptive on-time con - trollers, and usually takes the form of double-pulsing or esr loop instability. double-pulsing occurs due to switching noise seen at the fb input or because the fb ripple voltage is too low. this causes the fb comparator to trigger prematurely after the 250ns minimum of-time has expired. in extreme cases the noise can cause three or more successive on-times. double-pulsing will result in higher ripple voltage at the output, but in most applications it will not afect opera - tion. this form of instability can usually be avoided by providing the fb pin with a smooth, clean ripple signal that is at least 10mvp-p, which may dictate the need to increase the esr of the output capacitors. it is also impera - tive to provide a proper pcb layout as discussed in the layout guidelines section. another way to eliminate doubling-pulsing is to add a small (~ 10pf) capacitor across the upper feedback resis - tor, as shown in figure 13. this capacitor should be left unpopulated until it can be confrmed that double-pulsing exists. adding the c top capacitor will couple more ripple into fb to help eliminate the problem. an optional con - nection on the pcb should be available for this capacitor. v out to fb pin r 2 r 1 c top figure 13 capacitor coupling to fb pin esr loop instability is caused by insufficient esr. the details of this stability issue are discussed in the esr requirements section. the best method for checking sta - bility is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. ringing for more than one cycle after the initial step is an indication that the esr should be increased. one simple way to solve this problem is to add trace resis - tance in the high current output path. a side efect of adding trace resistance is a decrease in load regulation performance. esr requirements a minimum esr is required for two reasons. one reason is to generate enough output ripple voltage to provide 10mvp-p at the fb pin (after the resistor divider) to avoid double-pulsing. the second reason is to prevent instability due to insuf - cient esr. the on-time control regulates the valley of the output ripple voltage. this ripple voltage is the sum of the two voltages. one is the ripple generated by the esr, the other is the ripple due to capacitive charging and dis - charging during the switching cycle. for most applica - tions the minimum esr ripple voltage is dominated by the output capacitors, typically sp or poscap devices. for stability the esr zero of the output capacitor should be lower than approximately one-third the switching fre - quency. the formula for minimum esr is shown by the following equation. sw out min f c 2 3 sr e u u s u
sc403 26 applications information (continued) using ceramic output capacitors for applications using ceramic output capacitors, the esr is normally too small to meet the above esr criteria. in these applications it is necessary to add a small virtual esr network composed of two capacitors and one resistor, as shown in figure 14. this network creates a ramp voltage across c l , analogous to the ramp voltage generated across the esr of a standard capacitor. this ramp is then capaci - tively coupled into the fb pin via capacitor c c . r 1 r 2 fb pin c c c out l low - side high - side c l r l virtual esr network figure 14 virtual esr ramp circuit dropout performance the output voltage adjust range for continuous-conduc - tion operation is limited by the fixed 80ns (typical) minimum of-time of the one-shot. when working with low input voltages, the duty-factor limit must be calcu - lated using worst-case values for on and of times. the duty-factor limitation is shown by the next equation. ) max ( off ) min ( on ) min ( on t t t duty the inductor resistance and mosfet on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. system dc accuracy (v out controller) three factors afect v out accuracy: the trip point of the fb error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. the error comparator ofset is trimmed so that under static condi - tions it trips when the feedback pin is 750mv, + 1%. the on-time pulse from the sc403 in the design example is calculated to give a pseudo-fxed frequency of 300khz. some frequency variation with line and load is expected. this variation changes the output ripple voltage. because constant on-time converters regulate to the valley of the output ripple, ? of the output ripple appears as a dc regu - lation error. for example, if the output ripple is 50mv with v in = 6 volts, then the measured dc output will be 25mv above the comparator trip point. if the ripple increases to 80mv with v in = 25v, then the measured dc output will be 40mv above the comparator trip. the best way to mini - mize this efect is to minimize the output ripple. to compensate for valley regulation, it may be desirable to use passive droop. take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capaci - tor. this trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. passive droop minimizes the required output capaci - tance because the voltage excursions due to load steps are reduced as seen at the load. the use of 1% feedback resistors may result in up to 1% error. if tighter dc accuracy is required, 0.1% resistors should be used. the output inductor value may change with current. this will change the output ripple and therefore will have a minor efect on the dc output voltage. the output esr also afects the output ripple and thus has a minor efect on the dc output voltage. switching frequency variation the switching frequency will vary depending upon line and load conditions. the line variation is a result of fxed propagation delays in the on-time one-shot, as well as unavoidable delays in the external mosfet switching. as v in increases, these factors make the actual dh on-time slightly longer than the ideal on-time. the net efect is that frequency tends to falls slightly with increasing input voltage.
sc403 27 applications information (continued) the switching frequency also varies with load current as a result of the power losses in the mosfets and the induc - tor. for a conventional pwm constant-frequency con - verter, as load increases the duty cycle also increases slightly to compensate for ir and switching losses in the mosfets and inductor. a constant on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from v in as losses increase). the on-time is essen - tially constant for a given v out /v in combination, to ofset the losses the of-time will tend to reduce slightly as load increases. the net effect is that switching frequency increases slightly with increasing load.
sc403 28 applications information (continued) all other decoupling capacitors must be located as close as possible to the ic. pgnd plane pgnd requires its own copper plane with no other signal traces routed on it. copper planes, multiple vias and wide traces are needed to connect pgnd to input capacitors, output capacitors, and the pgnd pins on the device. the pgnd copper area between the input capacitors, output capacitors, and pgnd pins must be as tight and compact as possible to reduce the area of the pcb that is exposed to noise due to current fow on this node. connect pgnd to agnd with a short trace or 0 ? resistor. this connection should be as close to the device as possible. ? ? ? ? ? vout plane on top layer l cldo c in cff rfb 2 rfb 1 rilim c b s t rldo 2 rldo 1 lx plane on inner or bottom layer all components shown top side agnd plane on inner layer v in plane on inner or bottom layer rgnd agnd connects to pgnd close to the ic pin 1 marking ic with vias for lx , agnd , vin c out pgnd on inner or bottom layer pgnd pgnd on top layer v 5 v decoupling capacitor c v 5 v rgnd figure 15 pcb layout pcb layout guidelines the optimum layout for the sc403 is shown in figure 15. this layout shows an integrated fet buck regulator with a maximum current of 6a. the total pcb area is approxi - mately 20 x 25 mm. critical layout guidelines the following critical layout guidelines must be followed to ensure proper performance of the device. ic decoupling capacitors pgnd plane agnd island fb, vout, and other analog control signals bst, ilim, and lx cin and cout placement and current loops ic decoupling capacitors a 0.1 f capacitor must be located as close as possible to the ic and directly connected to pins 3 (vdd) and 4 (agnd). ? ? ? ? ? ? ?
sc403 29 applications information (continued) agnd island agnd should have its own island of copper with no other signal traces routed on this layer that connects the agnd pins and pad of the device to the analog control components. all of the components for the analog control cir - cuitry should be located so that the connections to agnd are done by wide copper traces or vias down to agnd. connect pgnd to agnd with a short trace or 0 ? resistor. this connection should be as close to the device as possible. fb, vout, and other analog control signals the connection from the v out power to the analog control circuitry must be routed from the output capacitors and located on a quiet layer. the traces between vout and the analog control circuitry (vout, and fb pins) must be short and routed away from noise sources, such as bst, lx, vin, and pgnd between the input capacitors, output capacitors, and the device. ilim and ton nodes must be as short as possible to ensure the best accuracy in current limit and on time. r ilim should be close to the device and connected to lx with a kelvin trace to pin 28 on the device. all of the lx pins are connected to the lx pad on the device, which should be a sufcient con - nection and will prevent the need to connect the resistor further into the lx plane. the feedback components for the switcher and the ldo need to be as close to the fb and fbl pins of the device as possible to reduce the pos - sibility of noise corrupting these analog signals. ? ? ? ? ? ? ? ? bst, ilim and lx lx and bst are very noisy nodes and must be routed to minimized the pcb area that is exposed to these signals. the connections for the boost capacitor between the device and lx must be short and directly connected to the lxbst (pin 13). the connections for the current limit resistor between the ilim pin and lx must be as short as possible and directly connected to pin 28 (lxs). the lx node between the ic and the inductor should be wide enough to handle the inductor current and short enough to eliminate the pos - sibility of lx noise corrupting other signals. multiple vias should be used to provide a good connection to lx between the device and the inductor. capacitors and current loops the current loops between the input capacitors, the device, the inductor, and the output capaci - tors must be as close as possible to each other to reduce ir drop across the copper. all bypass and output capacitors must be con - nected as close as possible to the pin on the device. soft-start capacitor the capacitor used for soft-start should be located away from the bst pin and its capacitor. if possible locate the boost capacitor on the opposite side of the board form the ic and soft- start capacitor. ? ? ? ? ? ? ? ? ? ?
sc403 30 outline drawing mlpq-5x5-32 b aaa c c seating plane 1 2 n bbb c a b coplanarity applies to the exposed pad as well as the terminals . controlling dimensions are in millimeters ( angles in degrees ). notes : 2 . 1 . a pin 1 indicator ( laser mark ) d e a 2 bxn a a 1 e lxn e 1 0 . 76 0 . 76 3 . 48 1 . 05 d 1 1 . 66 1 . 49 pin 1 identification r 0 . 20 3 . 61 millimeters 0 . 50 bsc . 002 - 0 . 00 . 000 a 1 . 193 . 193 . 135 . 076 . 012 . 007 e 1 aaa bbb n e l a 2 d 1 d e b . 020 bsc . 137 . 016 . 003 . 004 32 . 197 (. 008 ) . 078 . 197 . 010 - 3 . 43 . 139 . 020 0 . 30 . 201 . 201 . 080 - . 012 4 . 90 4 . 90 1 . 92 - 0 . 18 . 031 min dim a max dimensions inches - nom . 039 0 . 80 min - 0 . 05 5 . 10 5 . 10 3 . 53 2 . 02 0 . 50 0 . 30 3 . 48 0 . 40 0 . 10 0 . 08 32 5 . 00 ( 0 . 20 ) 1 . 97 5 . 00 0 . 25 - 1 . 00 max - nom
sc403 31 land pattern mlpq-5x5-32 1 . 74 3 . 48 h 2 k 3 . 61 h 1 k 1 y h ( c ) g this land pattern is for reference purposes only . consult your manufacturing group to ensure your notes : 2 . dim x y h k p c g millimeters inches ( 4 . 95 ) . 012 . 030 . 165 . 020 . 078 . 137 (. 195 ) 0 . 30 0 . 75 3 . 48 0 . 50 1 . 97 4 . 20 dimensions company ' s manufacturing guidelines are met . 5 . 70 . 224 z failure to do so may compromise the thermal and / or functional performance of the device . shall be connected to a system ground plane . thermal vias in the land pattern of the exposed pad 3 . 4 . square package - dimensions apply in both x and y directions . controlling dimensions are in millimeters ( angles in degrees ). 1 . x p z h 1 . 059 1 . 49 h 2 . 065 1 . 66 k 1 . 041 1 . 05 1 . 74
sc403 32 contact information semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com ? semtech 2010 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any conse - quence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellec - tual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specifed maximum ratings or operation outside the specifed range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life- support applications, devices or systems or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners.

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